Project Overview
| Role: Designer & Developer | Duration: 2021 | Organization: IGFAE / CERN |
The Challenge
The SPS accelerator delivers beam in 4.8-second spills within a 30-second super-cycle. The oscilloscope DAQ needed to arm only when beam is coming, translate signal levels between the accelerator’s LVDS and lab equipment’s NIM/TTL, implement busy logic during readout, and isolate everything galvanically to avoid ground loops. No off-the-shelf module handled this combination.
My Contribution
Designed and built a Trigger Interface Board from scratch:
- SN65MLVD204A quad LVDS receiver on the input stage, converting SPS timing signals (early warning, spill start, spill end) to CMOS levels
- High-speed optocouplers for galvanic isolation, protecting lab electronics from accelerator ground faults and eliminating ground-loop interference on timing measurements
- NIM-level outputs for the oscilloscope trigger, LEMO connections for the AIDA TLU, and an HDMI interface for EUDAQ busy/trigger handshake
- GPIO-controlled busy logic blocking trigger acceptance during oscilloscope readout, enabling deadtime-free operation during beam delivery
- Control software in C using the Linux hidraw interface, with a state machine coordinating spill signals and oscilloscope readout
Built around the Microchip MCP2210 USB-to-SPI/GPIO bridge (9 configurable GPIO lines, USB HID interface, no custom drivers needed).
Technical Stack
C PCB Design MCP2210 LVDS NIM USB HID Signal Conditioning Optocouplers
Results
- <1 μs trigger latency from spill-start edge to oscilloscope arm (negligible vs 4.8 s spill)
- Near-100% live-time during beam delivery, limited only by inter-spill oscilloscope readout
- Used across all three 2021 SPS campaigns (June H6, August H8, October H8) without hardware failures
- Zero custom driver installations required on control PCs (USB HID)
Industry Relevance
End-to-end hardware design project: requirements analysis, schematic design, signal conditioning, firmware development, and field deployment under demanding conditions. Directly applicable to test infrastructure design, embedded systems, industrial DAQ integration, and any role requiring bridging between heterogeneous hardware systems.